Why Graphics Programmers Need to Know About DRAM

Wednesday, 13 August 10:45 AM - 12:15 PM | Vancouver Convention Centre, East Building, Ballroom A

For applications like graphics, where data are often not cache-resident, optimizing for DRAM access is critical for improving both speed and power performance. The dramatic difference in speed and power of a DRAM access vs. an on-chip memory access means that even small changes in main-memory traffic and behavior can have a large impact on system performance. For example, many studies attribute 25-40% of total power consumed in a data center to the DRAM system. In the graphics domain, a proposed architecture for ray tracing with cache-hit-rate percentages in the 90s still shows almost 60% of the power consumed in the DRAM.

Optimizing for DRAM requires knowing something about the complex and subtle behavior of DRAM memory: understanding chip organization and functionality, organization of chips and data on a DIMM, and the behavior of the memory controller. This course presents examples of how much difference DRAM optimization can make in graphics programs, then describes the operation and behavior of DRAM memory that application programmers can take advantage of. It concludes with a description of a detailed DRAM simulator (USIMM) that can be used to add high-fidelity DRAM models to system simulations.





Intended Audience

Programmers who are interested in optimizing the overall performance of their applications, including memory behavior.


Erik Brunvand
University of Utah

Daniel Kopta
University of Utah

Niladrish Chatterjee
NVIDIA Corporation