Technical Papers

Hardware Systems

Thursday, 14 August 9:00 AM - 10:30 AM | Vancouver Convention Centre, East Building, Ballroom B-C Session Chair: Diego Nehab, Instituto de Matemática Pura e Aplicada

AMFS: Adaptive Multi-Frequency Shading for Future Graphics Processors

AMFS is a novel hardware architecture for pixel shading in GPUs, which enables efficient reuse of shading between primitives to drastically reduce the total cost. The shading rate is locally and automatically controlled, providing the user with full flexibility to scale performance vs quality.

Petrik Clarberg
Intel Corporation

Robert Toth
Intel Corporation

Jon Hasselgren
Intel Corporation

Jim Nilsson
Intel Corporation

Tomas Akenine-Möller
Intel Corporation, Lunds universitet

Extending the Graphics Pipeline with Adaptive, Multi-Rate Shading

An extensive study of the challenges of integrating adaptive, multi-rate shading into the real-time graphics pipeline. The paper proposes pipeline extensions for multi-rate fragment shading, design techniques for adaptive sampling in shaders, and a shading language for authoring shaders for this system.

Yong He
Carnegie Mellon University

Yan Gu
Carnegie Mellon University

Kayvon Fatahalian
Carnegie Mellon University

RayCore: A Ray-Tracing Hardware Architecture for Mobile Devices

This paper presents RayCore, a mobile ray-tracing hardware architecture. RayCore supports real-time ray tracing and tree construction for dynamic scenes. The architecture demonstrates high performance per unit area and unit energy.

Jae-Ho Nah
Sejong University

Hyuck-Joo Kwon
Sejong University

Dong-Seok Kim
Sejong University

Cheol-Ho Jeong
Siliconarts, Inc.

Jinhong Park
LG Electronics

Tack-Don Han
Yonsei University

Dinesh Manocha
University of North Carolina at Chapel Hill

Woo-Chan Park
Sejong University

Embree - A Ray Tracing Kernel Framework for Efficient CPU Ray Tracing

TBD

Ingo Wald
Intel Corporation

Sven Woop
Intel Corporation

Carsten Benthin
Intel Corporation

Greg Johnson
Intel Corporation

Manfred Ernst
Intel Corporation (now Google Inc.)

Darkroom: Compiling High-Level Image Processing Code into Hardware Pipelines

This paper presents a language that compiles high-level image-processing code to produce efficient ASIC and FPGA hardware and CPU code. Restrictions in the language allow scheduling the computation with all intermediates in local storage, eliminating unnecessary DRAM reads, and delivering high performance and energy efficiency on all targets.

James Hegarty
Stanford University

Zachary DeVito
Stanford University

John Brunhaver
Stanford University

Jonathan Ragan-Kelley
CSAIL MIT

Steven Bell
Stanford University

Artem Vasilyev
Stanford Univeristy

Noy Cohen
Stanford Univeristy

Mark Horowitz
Stanford University

Pat Hanrahan
Stanford University